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IRL1004PBF hexfet ? power mosfet pd - 95403 s d g parameter typ. max. units r jc junction-to-case ??? 0.75 r cs case-to-sink, flat, greased surface 0.50 ??? c/w r q ja junction-to-ambient ??? 62 thermal resistance v dss = 40v r ds(on) = 0.0065 ? i d = 130a logic-level gate drive advanced process technology ultra low on-resistance dynamic dv/dt rating 175c operating temperature fast switching fully avalanche rated fifth generation hexfet ? power mosfets from international rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. this benefit, combined with the fast switching speed and ruggedized device design that hexfet power mosfets are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. the to-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 watts. the low thermal resistance and low package cost of the to-220 contribute to its wide acceptance throughout the industry. description parameter max. units i d @ t c = 25c continuous drain current, v gs @ 10v 130 i d @ t c = 100c continuous drain current, v gs @ 10v 92 a i dm pulsed drain current 520 p d @t c = 25c power dissipation 200 w linear derating factor 1.3 w/c v gs gate-to-source voltage 16 v e as single pulse avalanche energy 700 mj i ar avalanche current 78 a e ar repetitive avalanche energy 20 mj dv/dt peak diode recovery dv/dt 5.0 v/ns t j operating junction and -55 to + 175 t stg storage temperature range soldering temperature, for 10 seconds 300 (1.6mm from case) c mounting torque, 6-32 or m3 srew 10 lbf?in (1.1n?m) absolute maximum ratings www.irf.com 1 to-220ab lead-free
IRL1004PBF 2 www.irf.com parameter min. typ. max. units conditions v (br)dss drain-to-source breakdown voltage 40 ??? ??? v v gs = 0v, i d = 250a ? v (br)dss / ? t j breakdown voltage temp. coefficient ??? 0.04 ??? v/c reference to 25c, i d = 1ma ??? ??? 0.0065 v gs = 10v, i d = 78a ??? ??? 0.009 v gs = 4.5v, i d = 65a v gs(th) gate threshold voltage 1.0 ??? ??? v v ds = v gs , i d = 250a g fs forward transconductance 63 ??? ??? s v ds = 25v, i d = 78a ??? ??? 25 v ds = 40v, v gs = 0v ??? ??? 250 v ds = 32v, v gs = 0v, t j = 150c gate-to-source forward leakage ??? ??? 100 na v gs = 16v gate-to-source reverse leakage ??? ??? -100 v gs = -16v q g total gate charge ??? ??? 100 i d = 78a q gs gate-to-source charge ??? ??? 32 nc v ds = 32v q gd gate-to-drain ("miller") charge ??? ??? 43 v gs = 4.5v, see fig. 6 and 13 t d(on) turn-on delay time ??? 16 ??? v dd = 20v t r rise time ??? 210 ??? i d = 78a t d(off) turn-off delay time ??? 25 ??? r g = 2.5 ? , v gs = 4.5v t f fall time ??? 14 ??? r d = 0.18 ? , see fig. 10 between lead, 6mm (0.25in.) from package and center of die contact c iss input capacitance ??? 5330 ??? v gs = 0v c oss output capacitance ??? 1480 ??? pf v ds = 25v c rss reverse transfer capacitance ??? 320 ??? ? = 1.0mhz, see fig. 5 electrical characteristics @ t j = 25c (unless otherwise specified) i gss i dss drain-to-source leakage current l d internal drain inductance ??? 4.5 ??? l s internal source inductance ??? 7.5 ??? r ds(on) static drain-to-source on-resistance a s d g source-drain ratings and characteristics repetitive rating; pulse width limited by max. junction temperature. (see fig. 11) i sd 78a, di/dt 370a/s, v dd v (br)dss , t j 175c notes: starting t j = 25c, l =0.23mh r g = 25 ? , i as = 78a. (see figure 12) pulse width 300s; duty cycle 2% calculated continuous current based on maximum allowable junction temperature; for recommended current-handling of the package refer to design tip #93-4 parameter min. typ. max. units conditions i s continuous source current mosfet symbol (body diode) ??? ??? showing the i sm pulsed source current integral reverse (body diode) ??? ??? p-n junction diode. v sd diode forward voltage ??? ??? 1.3 v t j = 25c, i s = 78a, v gs = 0v t rr reverse recovery time ??? 78 120 ns t j = 25c, i f = 78a q rr reverse recovery charge ??? 180 270 nc di/dt = 100a/s t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by l s +l d ) s d g 130 520 a
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IRL1004PBF www.irf.com 3 fig 1. typical output characteristics fig 3. typical transfer characteristics fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics -60 -40 -20 0 20 40 60 80 100 120 140 160 180 0.0 0.5 1.0 1.5 2.0 2.5 t , junction temperature ( c) r , drain-to-source on resistance (normalized) j ds(on) v = i = gs d 10v 130a 0.1 1 10 100 1000 10000 0.1 1 10 100 20s pulse width t = 25 c j top bottom vgs 15v 10v 7.0v 5.5v 4.5v 4.0v 3.5v 2.7v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 2.7v 1 10 100 1000 0.1 1 10 100 20s pulse width t = 175 c j top bottom vgs 15v 10v 7.0v 5.5v 4.5v 4.0v 3.5v 2.7v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 2.7v 0.1 1 10 100 1000 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 v = 50v 20s pulse width ds v , gate-to-source voltage (v) i , drain-to-source current (a) gs d t = 25 c j t = 175 c j 25
IRL1004PBF 4 www.irf.com fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 0 30 60 90 120 150 180 0 2 4 6 8 10 12 q , total gate charge (nc) v , gate-to-source voltage (v) g gs for test circuit see figure i = d 13 78 a v = 20v ds v = 32v ds 1 10 100 1000 10000 1 10 100 operation in this area limited by r ds(on) single pulse t t = 175 c = 25 c j c v , drain-to-source voltage (v) i , drain current (a) i , drain current (a) ds d 10us 100us 1ms 10ms 1 10 100 0 2000 4000 6000 8000 10000 v , drain-to-source voltage (v) c, capacitance (pf) ds v c c c = = = = 0v, c c c f = 1mhz + c + c c shorted gs iss gs gd , ds rss gd oss ds gd c iss c oss c rss 0.1 1 10 100 1000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v ,source-to-drain voltage (v) i , reverse drain current (a) sd sd v = 0 v gs t = 25 c j t = 175 c j
IRL1004PBF www.irf.com 5 fig 9. maximum drain current vs. case temperature fig 10a. switching time test circuit v ds 90% 10% v gs t d(on) t r t d(off) t f fig 10b. switching time waveforms
1 0.1 % 4.5v + - fig 11. maximum effective transient thermal impedance, junction-to-case 25 50 75 100 125 150 175 0 20 40 60 80 100 120 140 t , case temperature ( c) i , drain current (a) c d limited by package 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response)
IRL1004PBF 6 www.irf.com d.u.t. v ds i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - fig 13b. gate charge test circuit fig 12c. maximum avalanche energy vs. drain current 25 50 75 100 125 150 175 0 300 600 900 1200 1500 1800 starting t , junction temperature ( c) e , single pulse avalanche energy (mj) j as i d top bottom 32a 55a 78a fig 12a. unclamped inductive test circuit fig 12b. unclamped inductive waveforms v ds l d.u.t. v dd i as t p 0.01 ? r g + - t p v ds i as v dd v (br)dss 4.5 v q g q gs q gd v g charge fig 13a. basic gate charge waveform 4.5 v
IRL1004PBF www.irf.com 7 p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - fig 14. for n-channel hexfet ? power mosfets * v gs = 5v for logic level devices peak diode recovery dv/dt test circuit r g v dd ? dv/dt controlled by r g ? driver same type as d.u.t. ? i sd controlled by duty factor "d" ? d.u.t. - device under test d.u.t circuit layout considerations ? low stray inductance ? ground plane ? low leakage inductance current transformer *
IRL1004PBF 8 www.irf.com lead assignments 1 - gate 2 - drain 3 - source 4 - drain - b - 1.32 (.052) 1.22 (.048) 3x 0.55 (.022) 0.46 (.018) 2.92 (.115) 2.64 (.104) 4.69 (.185) 4.20 (.165) 3x 0.93 (.037) 0.69 (.027) 4.06 (.160) 3.55 (.140) 1.15 (.045) min 6.47 (.255) 6.10 (.240) 3.78 (.149) 3.54 (.139) - a - 10.54 (.415) 10.29 (.405) 2.87 (.113) 2.62 (.103) 15.24 (.600) 14.84 (.584) 14.09 (.555) 13.47 (.530) 3x 1.40 (.055) 1.15 (.045) 2.54 (.100) 2x 0.36 (.014) m b a m 4 1 2 3 notes: 1 dimensioning & tolerancing per ansi y14.5m, 1982. 3 outline conforms to jedec outline to-220ab. 2 controlling dimension : inch 4 heatsink & lead measurements do n ot include burrs. hexfet 1- gate 2- drain 3- source 4- drain lead assignments igbts, copack 1- gate 2- collector 3- emitter 4- collector

dimensions are shown in millimeters (inches)

example: in the assembly line "c" t his is an irf 1010 lot code 1789 as s e mb le d on ww 19, 1997 part number as s e mb l y lot code dat e code ye ar 7 = 1997 line c week 19 logo re ct if ie r int e rnat ional note: "p" in assembly line position indicates "lead-free" data and specifications subject to change without notice. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 06/04
note: for the most current drawings please refer to the ir website at: http://www.irf.com/package/

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